1. Field of the Invention
This invention relates to an amplifier with a plurality of stages in cascade connection having very high gain, including a first pair of bipolar transistors connected in first long-tailed-pair configuration, a second pair of field-effect transistors connected in second long-tailed-pair configuration in cascade connection after the first long-tailed pair, and constant current generator collector load means for the first long-tailed pair, and more particularly to such an amplifier wherein the gain of the first long-tailed-pair configuration is substantially equal to the maximum available voltage gain.
2. Description of the Prior Art
In a typical prior art plural-stage amplifier, the initial stage of which is a long-tailed-pair connection of transistors, the voltage gain is determined by the transconductances of those transistors and the resistances of the load elements, including the input resistance of the subsequent amplifier stage, which resistances are low relative to the collector resistances of the transistors in the initial long-tail pair. A simplified mathematical expression for this voltage gain is: EQU A=g.sub.m R.sub.L [ 1]
where g.sub.m is the transconductance of the transistor, and R.sub.L is the effective resistance of the load elements paralleled with the input resistance of the following amplifier stage and the collector resistances of the transistors in the long-tailed pair. Because the transconductance g.sub.m is proportional to the emitter current of the transistor, while R.sub.L is substantially independent of that current, the gain A also varies in response to that current. Environmental or parameter variations may also cause changes in A that have a deleterious effect on the amplifier performance. Such variations may be difficult to predict or characterize, thereby making the amplifier much more difficult to apply and, therefore, less desirable. Significant variations in A will adversely affect other characteristics of the amplifier, for example, offset voltage error and common-mode rejection ratio.
The "output offset voltage error" of an amplifier is the deviation of the output DC level from a desired level when both amplifier input terminals are shorted together. Offset voltage error is commonly stated as being referred to the input terminals. This "input offset voltage error" may be defined as that DC input voltage necessary to cause the value of the DC output voltage to equal an arbitrary value, this arbitrary value generally equalling a reference potential commonly midway between the relatively positive and relatively negative operating potentials applied to the amplifier output stage. The input offset voltage error is generally equal to the output offset voltage error divided by the voltage gain of the amplifier.
In operational amplifiers, which typically include a plurality of cascaded amplifier stages, offset voltage error represents an accumulation of imbalances between elements in the input-output signal paths. For example, the difference in the base-emitter operating voltages of bipolar transistors connected in long-tailed-pair configuration provides a signal voltage which contributes to the offset voltage error of that stage. Similar errors introduced in each subsequent stage contribute to the total offset voltage error which comprises the sum of the products of the offset voltage errors of each stage multiplied by the gain of the amplifier between the stage and the output. Output offset voltage error (V.sub.os) is given by ##EQU1## where: Vos.sub.i is the input offset voltage error of the ith stage, and A.sub.i is the voltage gain of the ith stage. In a typical example, all of the Vos.sub.i may be of similar order of magnitude. Then, if the gain A.sub.1 is very large relative to the other gains A.sub.i, equation [3] effectively reduces to EQU V.sub.os =A.sub.1 Vos.sub.1. [4]
Thus, the offset voltage error of the cascade amplifier is dominated by the parameters of a single amplifier stage, preferably, the input amplifier stage.
Offset voltage errors have an undesirable effect on amplifier performance. Offset voltage errors are indistinguishable from the desired error voltages developed by direct-coupled voltage feedback when the amplifier is used to provide direct-coupled amplification. If the amplifier is to function as a comparator, offset voltages introduce errors in the switching characteristics, causing switching to occur at a signal level different from that desired. Clearly, minimizing offset voltage error is desirable to obtain best performance from the amplifier.
Similarly, cascade amplifiers ordinarily should be designed to have a low-noise, high-gain, first stage which substantially determines the noise-figure of the entire amplifier. Analysis of noise performance is analogous to the analysis of equations [2] through [4] hereinabove with mean-square noise voltages e.sub.n.sbsb.1.sup.2 substituted for offset voltages Vos.sub.i. Ordinarily, low-noise bipolar transistors are preferred in a low-noise, high-gain first amplifier stage, components tending to contribute more noise (for example, field-effect transistors and high-ohmic value resistors) are to be avoided, particularly in the first amplifier stage.
In a cascade amplifier having differential inputs, design of the input stage in balanced long-tail-pair configuration with high gain has a material beneficial effect on the common-mode rejection ratio (CMRR) which is the ratio of the gain of the amplifier circuit in response to differential-mode input signals (A.sub.d) to its gain in response to common-mode input signals (A.sub.c), i.e., EQU CMRR=A.sub.d /A.sub.c. [5]
As is well known to those skilled in the art, the common-mode signal is the instantaneous algebraic average of two signals applied to a balanced circuit, both signals being referred to a common reference.
Prior art amplifiers have employed constant current source loading of long-tailed-pair transistor amplifiers to generally increase the gain thereof--e.g., as shown in U.S. Pat. No. 3,614,645 issued to C. F. Wheatley. Ordinarily, the base electrodes of bipolar transistors in the following amplifier stage are connected to receive the signal from the collectors of the transistors of the first long-tailed pair. The input resistance of the subsequent amplifier stage is low as compared to the collector resistance of the transistors of the first long-tailed pair, and limits the maximum voltage gain that can be achieved with the first long-tailed pair. Therefore, using cascode-connected transistors to form constant current loads tending to have higher output resistance, will not result in increased voltage gain from the first long-tailed pair.
Application Brief 136, "A Low-Drift, Low-Noise Monolithic Operational Amplifier For Low Level Signal Processing," Fairchild Semiconductor, July, 1969, recommends that the simplest input amplifier configuration possible be used to realize minimum offset voltage error, specifically, two differentially connected transistors having well-matched resistors as the collector loads. Active collector loads should be avoided, according to this reference, because they do not exhibit matching or temperature-tracking characteristics comparable to resistive loads. Such embodiments are severely limited by achievable first stage gain and resistor noise, and therefore have inferior offset voltage and noise performance. The present inventor has discerned that further improvement is achieved by amplifiers, in accordance with his invention, whose first stages have low-noise bipolar transistors and achieve substantially the maximum available voltage gain offered by those transistors.
U.S. Pat. No. 3,644,838 issued to S. Graf, shows an amplifier having bipolar NPN transistors forming a long-tailed-pair first amplifier stage having MOS FET transistor current source active loads, and having P-channel MOS field-effect transistors forming a subsequent amplifier stage. Because the subsequent stage has comparatively low input resistance at the source electrodes of the MOS FET transistors, it prevents the first long-tailed-pair amplifier from realizing or achieving its maximum available voltage gain.
U.S. Pat. No. 3,953,807 issued to O. H. Schade, Jr., illustrates a single-ended, direct-coupled, inverting amplifier output stage having a bipolar transistor with active current source load driving the gate electrode input to a subsequent FET amplifier stage. That configuration, however, is limited to a single-ended output amplifier stage not having an emitter current supply. The present inventor has discerned the need and provided solutions for maintaining substantial equality between the emitter current and the active current-source load current of the bipolar transistor. In the present invention, Schade's technique is extended to a differentially configured amplifier stage and, in particular, to the initial stages of a cascade amplifier to realize improvements in offset voltage error, noise figure, and common-mode rejection ratio not otherwise obtainable.